1. Field of the Invention
The present invention relates to a pipeline A/D converter that converts an analog input signal into a digital signal in descending order of bit significance by using a plurality of stages, each of which quantizes the analog input signal so as to generate the digital signal.
2. Description of Related Art
As digitization proceeds in the fields of audiovisual, telecommunication, and the like, it has been required for A/D converters used as key devices in these fields to achieve higher speed and higher resolution. Pipeline A/D converters recently have been used frequently as circuits that are excellent in terms of high speed and power consumption. However, as CCD cameras have an increasing number of pixels, for example, pipeline A/D converters that are excellent in terms of high speed and power consumption also are required to achieve much higher speed and lower power consumption.
FIG. 2 is a block diagram showing a configuration of a basic pipeline A/D converter. This pipeline A/D converter includes n stages, i.e., a first stage 1[1] to an n-th stage 1[n], connected in cascade, and a flash AD converter 2 in a final stage. An input analog signal Vin is converted into a digital signal one bit by one bit by each of the n stages in descending order of bit significance, and the digital signal thus obtained is combined with an output digital signal from the flash AD converter 2, whereby an output digital signal is obtained as a result of converting the input analog signal Vin at a desired bit number.
Although FIG. 2 shows a specific configuration of only the first stage 1[1], the other stages also have the same configuration. That is, each of the stages includes an AD conversion portion 3, a DA conversion portion 4, and a remainder operation portion 5.
The AD conversion portion 3 converts the input analog signal supplied to a current stage into a ternary digital signal, and outputs the same. This digital signal also is supplied to the DA conversion portion 4. The DA conversion portion 4 converts the digital signal output from the AD conversion portion 3 into an analog signal so as to generate an analog reference signal, and supplies the same to the remainder operation portion 5. The remainder operation portion 5 subtracts the analog reference signal output of the DA conversion portion 4 from the input analog signal supplied to the current stage, and amplifies the obtained analog signal, thereby generating a remainder analog signal. The output signal from the remainder operation portion 5 is supplied to a subsequent stage as an input analog signal.
FIG. 3A shows a specific configuration for achieving a predetermined function by the DA conversion portion 4 and the remainder operation portion 5. The DA conversion portion 4 includes a logical operation portion 6 and a voltage supply portion 7. Other components, i.e., an operational amplifier 8, an input capacitor Cs, a feedback capacitor Cf, and switches 9 to 11, configure the remainder operation portion 5 in FIG. 2. The analog reference signal output from the DA conversion portion 4 is supplied to a connection node between the input capacitor Cs and the switch 9. In the following description, the capacitance values of the input capacitor Cs and the feedback capacitor Cf are represented by Cs and Cf, respectively.
The voltage supply portion 7 has three switches connected with three reference voltages +Vref, 0 V, and −Vref, respectively. The logical operation portion 6 outputs a signal for switching the switches of the voltage supply portion 7 based on the value of the digital signal output from the AD conversion portion 3. Thus, in the voltage supply portion 7, one of the three reference voltages is selected in accordance with the value of the digital signal, and an analog reference signal Vdac is supplied to the input capacitor Cs.
Next, an operation of this circuit will be described. In FIG. 3A, a clock Φ1 and a dock Φ2 take a high level (H) value and a low level (L) value mutually exclusively. When the clock Φ1 is H and the clock Φ2 is L, the switches 9 and 10 are ON and the switch 11 is OFF, so that an input analog signal Vin is sampled by the input capacitor Cs.
When the dock Φ1 is L and the dock Φ2 is H, the switches 9 and 10 are OFF and the switch 11 is ON, so that the electric charge sampled by the input capacitor Cs is redistributed to the input capacitor Cs and the feedback capacitor Cf. Further, the logical operation portion 6 is operated, so that the voltage supply portion 7 supplies the analog reference signal Vdac to the input capacitor Cs. As a result, the operational amplifier 8 outputs an output signal Vout expressed as follows.Vout={(Cs+Cf)/Cf}·Vin−(Cs/Cf)·Vdac  (1)When Cs=Cf, the following formula is satisfied.Vout=2·Vin−Vdac  (2)
The output signal Vout from the operational amplifier 8 will be described also with reference to FIG. 3B. In FIG. 3B, a horizontal axis represents the input analog signal Vin to each of the stages. A vertical axis represents the output signal Vout from the operational amplifier 8. As shown in the figure, the level of the input analog signal Vin on the horizontal axis is divided into a first region (−Vref to −Vref/4), a second region (−Vref/4 to +Vref/4), and a third region (+Vref/4 to +Vref).
The AD conversion portion 3 generates the ternary digital signal from the input analog signal Vin by using the reference voltage corresponding to a boundary of each of the regions. Based on the output digital signal from the AD conversion portion 3, the logical operation portion 6 controls the voltage supply portion 7 so that one of the voltages +Vref, 0 V, and −Vref is output corresponding to each of the first to third regions. Further, as a result of the operation of the above-described formula (2), the output signal Vout from the operational amplifier 8 with respect to the input analog signal Vin is as shown in FIG. 3B.
As described above, the analog reference signal is generated in accordance with the level of the input analog signal Vin, and addition/subtraction is performed with respect to the input analog signal Vin, whereby the output signal Vout from the operational amplifier 8 can be prevented from exceeding an input range of the AD conversion portion 3 in a subsequent stage.
Based on the pipeline A/D converter as described above, it has been known to revise the configure such that the first stage has a multi-bit configuration, i.e., performs conversion of a plurality of bits, so as to reduce power consumption (see JP 2007-324834 A, for example). More specifically, as shown in FIG. 4, conversion functions of the first to third stages 1[1] to 1[3] in the basic configuration in FIG. 2 are integrated into one first stage 12, in which an AD conversion portion 3a, a DA conversion portion 4a, and a remainder operation portion 5a are modified in accordance with such a function.
In the pipeline structure, the operational amplifiers in the respective stages consume a dominant amount of power. In view of this, when the first stage 12 has a multi-bit configuration as shown in FIG. 4, it becomes possible to perform conversion that has been performed in the three stages in the basic configuration with one operational amplifier, thereby serving to reduce power consumption.
In order for a first stage to have a multi-bit configuration, it is necessary to modify the function of the stage as shown in FIGS. 5A and 5B. More specifically, the functions of the three stages in the basic configuration shown in FIG. 5A are integrated into one stage as shown in FIG. 5B. The outputs from the remainder operation portions 5[1] to 5[3] in FIG. 5A are represented by transfer functions 13[1] to 13[3], respectively. Note here that the transfer functions 13[2] and 13[3] show the functions from the first stage collectively. The transfer function 13[1] output from the remainder operation portion 5[1] in the first stage, which is the same as that shown in FIG. 3B, corresponds to the ternary digital signal output from the AD conversion portion.
The transfer function 13[2] output from the remainder operation portion 5[2] in the second stage corresponds to a septenary digital signal, and the transfer function 13[3] output from the remainder operation portion 5[3] in the third stage corresponds to a quindecimal digital signal. FIG. 5B shows that the one remainder operation portion 5a achieves the functions of the three stages in FIG. 5A. To this end, the remainder operation portion 5a needs to perform eight-fold amplification, while the remainder operation portions 5[1] to 5[3] in FIG. 5A perform two-fold amplification.
However, when the first stage has a multi-bit configuration, the DA conversion portion used in the first stage becomes exponentially larger in size. This will be described with reference to FIGS. 6A and 6B. FIG. 6A shows a stage with a multi-bit configuration. This stage includes an AD conversion portion 14, a logical operation portion 15, voltage supply portions 16[1] to 16[16], an operational amplifier 8, input capacitors Cs, a feedback capacitor Cf, and switches 17 and 18.
The sixteen input capacitors Cs, which are connected in parallel with each other, are used, and an input analog signal Vin is supplied to first ends thereof and the other ends thereof are connected to an input terminal of the operational amplifier 8. The switch 17 is inserted in one end of each of the input capacitors Cs. The sixteen voltage supply portions 16[1] to 16[16] and the logical operation portion 15 configure a DA conversion portion, and the operational amplifier 8, the input capacitors Cs, the feedback capacitor Cf, and the switches 17 and 18 configure a remainder operation portion.
As shown in FIG. 6A, the voltage supply portion 16[1] includes two switches 19a and 19b. A high-potential reference voltage VRT and a low-potential reference voltage VRB are supplied to input sides of the switches 19a and 19b, respectively. Output sides of the switches 19a and 19b are connected to a connection node between any pair of the input capacitor Cs and the switch 17. The switches 19a and 19b are switched by the logical operation portion 15 in accordance with a digital signal output from the AD conversion portion 14. The other voltage supply portions 16[2] to 16[16] also have the same configuration.
With this configuration, each of the voltage supply portions 16[1] to 16[16] selectively outputs either of the two reference voltages VRT and VRB in accordance with the output from the AD conversion portion 14. As a result, based on a combination of the respective reference voltages supplied from the voltage supply portions 16[1] to 16[16] to the sixteen input capacitors Cs, practically, a quindecimal analog reference signal Vdac in accordance with the output from the AD conversion portion 14 is supplied to the reminder operation portion. The reminder operation portion is operated basically in the same manner as described with reference to FIG. 3A, and outputs a transfer function based on the quindecimal quantization as shown in FIG. 5B.
The table of FIG. 6B shows the relationship between a combination of the reference voltages VRT and VRB selected by the voltage supply portions 16[1] to 16[16] and the value of the analog reference signal Vdac. In the table, A to O (E to M are not shown) shown in the leftmost column correspond to the levels of the input analog signal Vin, more specifically, to fifteen values obtained as a result of the quantization by the AD conversion portion 14. Further, (−7) to (+7) ((−5) to (+3) are not shown) shown in the rightmost column represent the relative levels of the analog reference signal Vdac. The voltage supply portions (1 to 16) in the uppermost column correspond to the voltage supply portions 16[1] to 16[16], and the reference voltage selected by the switches 19a and 19b is shown in a lower column of each of the voltage supply portions. More specifically, “−1” shows that the reference voltage VRB is selected, while “1” shows that the reference voltage VRT is selected.
As described above, in order to perform A/D conversion of three bits, it is necessary to generate the analog reference signal Vdac at fifteen levels from (−7) through 0 to (+7), and this requires the use of sixteen voltage supply portions 16[1] to 16[16]. In general, the number of the voltage supply portions to be required is determined as 2(M+1) in accordance with the number of bits (M) to be converted in the current stage. Accordingly, the DA conversion portion becomes exponentially larger, which leads to disadvantages such as an increase in the area of an element, an increase in the complexity of wiring, and difficulty in routing wiring in a layout.
Further, in the case of a multi-bit configuration, the capacitance value of the input capacitors Cs is divided equally by the number of the voltage supply portions. Namely, in the case of the configuration in FIG. 6A, the capacitance value of the input capacitor Cs is set to be ½(M+1) times a total capacitance value. When one unit of the capacitors is small in size, relative accuracy decreases, which appears as an error of the pipeline A/D converter. Thus, in order to satisfy relative accuracy, it is necessary to increase a total capacitance, which also contributes to an increased area of an element.